1. Field Of The Invention
This invention relates to computer memory management units and, more particularly, to apparatus for increasing the number of hits which occur in a translation lookaside buffer portion of a memory management unit.
2. History Of The Prior Art
A virtual memory system is one which allows addressing of very large amounts of memory as though all of that memory were the main memory of the computer system even though actual main memory may consist of some substantially lesser amount of storage space. For example, main memory may consist of one megabyte of random access memory while sixty-four megabytes of memory are addressable using the virtual memory addressing system.
Virtual memory systems accomplish this feat by providing memory management units which translate virtual memory addresses into physical memory addresses. A particular physical address may be in main memory or in long term storage. If the physical address of information sought is in main memory, the information is accessed and utilized by the computer. If the physical address is in long term storage, the information is transferred to main memory where it may be used.
The basic memory management unit uses lookup tables which are stored in main memory. Any virtual address presented to the memory management unit is compared to the values stored in these tables to determine the physical address to access. There are often several levels of tables, and the comparison takes a great deal of system clock time.
To overcome this delay, virtual memory systems often include cache memories which use very fast components to store recently used data and instructions. These cache memories are usually connected so that they are rapidly accessible to the processors. These caches are first looked to by a processor before going to main memory for any information. The theory of these caches is that information most recently used is more likely to be needed again before other information is needed. This theory is valid, and many systems using cache memories have hit rates of over ninety percent.
These cache memories must also be addressed to obtain the information they contain. If these caches are addressed using physical addresses, then address translation is required before they may be accessed. To accomplish this without going through the page lookup tables, a typical memory management unit uses a translation lookaside buffer (TLB) to cache virtual page addresses which have been recently accessed along with their related physical page addresses. Such an address cache works on the same principle as do caches holding data and instructions, the most recently used addresses are more likely to be used than are other addresses. When provided a virtual address which it holds, the translation lookaside buffer furnishes a physical address for the information. If that physical address is in the related cache, then the information is immediately available to the processor without the necessity of going through the time consuming process of referring to the page lookup tables in main memory.
If when the processor sends a virtual address to the translation lookaside buffer, the address is not included in the translation lookaside buffer, then the memory management unit must retrieve the physical address using the lookup tables in main memory. When the physical address is recovered, it is stored along with the virtual address in the translation lookaside buffer so that the next time it is needed it is immediately available. When the information is recovered, it is stored in the cache under the physical address. This saves a great deal of time on the next use of the information because a typical lookup in the page tables may take from ten to fifteen clock cycles at each level of the search, while accessing the information using the translation lookaside buffer and the caches may require only one or two clock cycles.
U.S. patent application Ser. No. 07/631,966, entitled TRANSLATION LOOKASIDE BUFFER, filed Dec. 21, 1990, and assigned to the assignee of this invention, describes a translation lookaside buffer for a very fast RISC computer system which provides separate caches for data and for instructions. In a typical prior art computer system these different virtual addresses would be translated by separate hardware resources. The translation lookaside buffer described, however, stores virtual and physical addresses for data, instructions, and input/output operations. Such a translation lookaside buffer allows the very rapid translation of all virtual addresses which might be used by a system with a very minimum amount of hardware. Such a system is well adapted to be used in a system in which most of the hardware is resident on a single chip.
One problem which occurs in a system which uses physical addressing for instruction and data caches and which processes data, instruction, and input/output addresses through a single translation lookaside buffer is occasioned by the fact that addresses for data, instructions, and input/output operations may all contest for the translation lookaside buffer at the same time. When this occurs, the system must somehow provide for translating all of the addresses. If the translations are done serially, significant delays occurs. The provision of a separate translation lookaside buffer to handle the overflow adds a great deal of hardware which the aforementioned invention was designed to eliminate. Other possibilities such as prefetching instructions or speeding the operation of the translation lookaside buffer offer other undesirable levels of complication.